Within the field of electrical digital systems is a category of systems known as state machines. A state machine is a digital logic device that sequences (based on a timing reference signal) through a finite set of logical states which can have inputs and outputs. The outputs of the state machine are a function of the present state that the state machine is located within and the inputs received by the state machine. The state machine is implemented in fixed digital logic, and can be synthesized from a high-level design language such as VHDL or Verilog.
FIG. 1A is a state diagram illustrating an example of three different states that an exemplary state machine sequences through as it performs its operations. Once initialized, the state machine represented by FIG. 1A begins its operation within logical state 100. While within logical state 100, the state machine generates outputs 100a. Upon subsequent clock cycles, the state machine remains within logical state 100 generating outputs 100a, represented by conditional transition term arrow 106, until it receives a predetermined input condition. A conditional transition term causes the outputs of the state machine or its transition into another state to be dependent upon receiving a predetermined input condition while in a particular present state. Therefore, if the state machine receives the predetermined input condition while in state 100, it enters logical state 102 represented by state transition arrow 108. Upon entering state 102, the state machine generates outputs 102a. On subsequent clock cycles, the state machine remains within state 102 generating outputs 102a, represented by conditional transition term arrow 110, until it receives another predetermined input condition. If the state machine receives the predetermined input condition, the state machine enters logical state 104 represented by state transition arrow 112.
Once within logical state 104 of FIG. 1A, the state machine generates outputs 104a for a predetermined amount of time and then re-enters logical state 100, represented by state transition arrow 114. While in state 104, the state machine is not dependent on the receipt of any type of input condition to allow it to enter state 100. Instead, the state machine only remains within state 104 for a predetermined amount of time and then enters state 100. Alternatively, the state transition into state 100 can be based on input conditions. Once the state machine enters state 100, it continues to repeat the sequence of operations described above.
FIG. 1B is a block diagram illustrating a standard prior art synchronous state machine circuit 50. Within state machine combinatorial logic 122 is the state machine logic that causes state machine 50 to sequence through various predetermined states of operation. To more fully understand the operation of the standard prior art state machine 50, the state diagram illustrated within FIG. 1A will be discussed in conjunction with FIG. 1B.
Before the prior art synchronous state machine circuit 50 of FIG. 1B starts operations, it first is initialized. During the initialization of prior art state machine 50, the value that identifies the starting present state of state machine 50 (e.g., logical state 100 of FIG. 1A) is stored within state register 124 of FIG. 1B while the values that identify the outputs of state machine 50 (e.g., outputs 100a) are cleared within output register (latch) 126. Several data bits can be stored within output register 126, each identify different outputs of the state machine. For example, eight bits of data stored within output register 126 could identify eight outputs of state machine 50.
Once initialized, the prior art state machine circuit 50 starts operations within state 100 of FIG. 1A. State register 124 (latch) of FIG. 1B transfers the stored present state value to combinatorial logic 122 over the present state bus 136. At the same time the contents of state register 124 are transferred, the outputs of state machine 50 stored within output register 126 (e.g., outputs 100a) are transferred over output bus 132. State register 124 and output register 126 are both connected to a clock signal by bus 138, which causes both registers to have synchronous operations. State machine circuit 50 of FIG. 1B remains within the present state (e.g., state 100) performing the outputs (e.g., outputs 100a) until a predetermined input condition is received by combinatorial logic 122 over input bus 128.
Once the predetermined input condition is received over input bus 128, combinatorial logic 122 of FIG. 1B transfers to state register 124 the next state value that state machine 50 will be entering (e.g., state 102) over next state bus 134. At the same time combinatorial logic 122 transfers the next state value over bus 134, it also transfers to output register 126 the values that identify the outputs of state machine 50 (e.g., outputs 102a) over next output bus 130. Upon the next clock, state register 124 transfers the present state value to combinatorial logic 122 over the present state bus 136. Output register 126 transfers the outputs of state machine 50 over outputs bus 132. State machine 50 of FIG. 1B remains in state 102 until a predetermined input condition is received by combinatorial logic 122 over input bus 128.
Once the predetermined input condition is received over input bus 128, combinatorial logic 122 of FIG. 1B transfers to state register 124 the next state value that state machine 50 will be entering (e.g., state 104 of FIG. 1A) over next state bus 134. At the same time combinatorial logic 122 transfers the next state value, it also transfers to output register 126 the values that identify the outputs (e.g., outputs 104a) of state machine 50 over next output bus 130. Upon the next clock, state register 124 transfers the present state value to combinatorial logic 122 over the present state bus 136. Output register 126 transfers the outputs of state machine 50 over output bus 132. Once state machine 50 of FIG. 1B enters state 100, it continues to repeat the sequence of operations described above.
State machines are useful in electrical digital systems, but there are several disadvantages associated with state machines. State machines can be complicated. Moreover, the heart of the state machine design is the combinatorial logic, which after fabrication in silicon is modifiable only by difficult and manual methods. These difficult methods include the tedious and error prone task of making changes to the interconnect layers of the die itself. State machines can also have many boundary conditions and corner cases that are difficult to test during simulations which are performed before fabricating the state machine in silicon. Therefore, it would be advantageous to provide a circuit and system for correcting these errors post-fabrication. Furthermore, a designer of a state machine may find that after the state machine has been designed and fabricated, especially if the design was developed quickly for a prototype, that he or she desires to change the behavior of the state machine. Therefore, it would be advantageous to provide a system that allows the behavior of a state machine to be readily modified after it has been fabricated within silicon. The present invention provides these advantages and others not necessary recited above but clear within discussions of the present invention to follow.